cxl/acpi: Map component registers for Root Ports

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This implements the TODO in cxl_acpi for mapping component registers.
cxl_acpi becomes the second consumer of CXL register block enumeration
(cxl_pci being the first). Moving the functionality to cxl_core allows
both of these drivers to use the functionality. Equally importantly it
allows cxl_core to use the functionality in the future.

CXL 2.0 root ports are similar to CXL 2.0 Downstream Ports with the main
distinction being they're a part of the CXL 2.0 host bridge. While
mapping their component registers is not immediately useful for the CXL
drivers, the movement of register block enumeration into core is a vital
step towards HDM decoder programming.

Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
[djbw: fix cxl_regmap_to_base() failure cases]
Link: https://lore.kernel.org/r/164298415080.3018233.14694957480228676592.stgit@dwillia2-desk3.amr.corp.intel.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>

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This commit is contained in:

Ben Widawsky 2022-01-23 16:29:10 -08:00 • committed by Dan Williams

parent 8baa787b93

commit 303ebc1b17

5 changed files with 80 additions and 54 deletions

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13

drivers/cxl/acpi.c

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56

drivers/cxl/core/regs.c

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4

drivers/cxl/cxl.h

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52

drivers/cxl/pci.c

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9

drivers/cxl/pci.h

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