ARM: dts: exynos: Add bus nodes using VDD_INT for Exynos3250

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This patch adds the bus nodes using VDD_INT for Exynos3250 SoC.
Exynos3250 has following AXI buses to translate data between
DRAM and sub-blocks.

Following list specifies the detailed relation between DRAM and sub-blocks:
- ACLK400 clock for MCUISP
- ACLK266 clock for ISP
- ACLK200 clock for FSYS
- ACLK160 clock for LCD0
- ACLK100 clock for PERIL
- GDL clock for LEFTBUS
- GDR clock for RIGHTBUS
- SCLK_MFC clock for MFC

Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>

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Chanwoo Choi 2016-04-11 12:57:51 +09:00 • committed by Krzysztof Kozlowski

parent e9a53680de

commit 304d10abb6

1 changed files with 147 additions and 0 deletions

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arch/arm/boot/dts/exynos3250.dtsi

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