drm/i915/psr: LunarLake PSR2_CTL[IO Wake Lines] is 6 bits wide

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On LunarLake  PSR2_CTL[IO Wake Lines] contains now bit 13:18. Take this
into account when enabling PSR2_CTL.

Bspec: 69885

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240517073005.2414293-3-jouni.hogander@intel.com

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This commit is contained in:

Jouni Högander 2024-05-17 10:30:04 +03:00

parent 45430e7b7c

commit 30dee753ca

2 changed files with 6 additions and 0 deletions

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2

drivers/gpu/drm/i915/display/intel_psr.c

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4

drivers/gpu/drm/i915/display/intel_psr_regs.h

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