parisc: Also flush data TLB in flush_icache_page_asm

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commit 5035b230e7 upstream.

This is the second issue I noticed in reviewing the parisc TLB code.

The fic instruction may use either the instruction or data TLB in
flushing the instruction cache.  Thus, on machines with a split TLB, we
should also flush the data TLB after setting up the temporary alias
registers.

Although this has no functional impact, I changed the pdtlb and pitlb
instructions to consistently use the index register %r0.  These
instructions do not support integer displacements.

Tested on rp3440 and c8000.

Signed-off-by: John David Anglin  <dave.anglin@bell.net>
Signed-off-by: Helge Deller <deller@gmx.de>
Signed-off-by: Ben Hutchings <ben@decadent.org.uk>

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John David Anglin 2016-11-24 20:18:14 -05:00 • committed by Ben Hutchings

parent c2bf3d858e

commit 3136a9a1cc

1 changed files with 22 additions and 15 deletions

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arch/parisc/kernel/pacache.S

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