drm/amd/display: Set phy_mux_sel bit in dmub scratch register

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[Why]
B0 has pipe mux for DIGC and DIGD which can be connected to PHYF/PHYG or
PHYC/PHY D.

[How]
Based on chip internal hardware revision id determine it is B0 and set
DMUB scratch register so DMUBFW can connect the display pipe is
connected correctly to the dig.

Cc: Wayne Lin <wayne.lin@amd.com>
Cc: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Hansen <Hansen.Dsouza@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

...

This commit is contained in:

Hansen 2021-09-09 15:12:32 -04:00 • committed by Alex Deucher

parent a9a1ac4407

commit 3137f792c5

5 changed files with 9 additions and 3 deletions

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2

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

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1

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

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6

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

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2

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

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1

drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c

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