riscv: smp: Clarify comment "cache" -> "instruction cache"

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local_flush_icache_all() only flushes and synchronizes the *instruction*
cache, not the data cache. Since RISC-V does have a cbo.flush
instruction for data cache flush, clarify the comment to avoid
confusion.

Fixes: 58661a30f1 ("riscv: Flush the instruction cache during SMP bringup")
Signed-off-by: Vivian Wang <wangruikang@iscas.ac.cn>
Link: https://patch.msgid.link/20260204-riscv-smp-comment-update-2026-01-v1-2-8b77aa181530@iscas.ac.cn
Signed-off-by: Paul Walmsley <pjw@kernel.org>

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Vivian Wang 2026-04-04 18:42:40 -06:00 • committed by Paul Walmsley

parent fe0cf82fde

commit 31454cb5f1

1 changed files with 2 additions and 2 deletions

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arch/riscv/kernel/smpboot.c

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