ARM: dts: microchip: sama7g5: Add cache configuration for cpu node

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Describe the cache memories according with datasheet chapter 15.2:

- L1 cache configuration with 32KB for both data and instruction cache.
- L2 cache configuration with 256KB unified cache.

Before this patch the kernel reported the warning:

[    0.171425] cacheinfo: Unable to detect cache hierarchy for CPU 0

Signed-off-by: Mihai Sain <mihai.sain@microchip.com>
Link: https://lore.kernel.org/r/20250619070636.8844-3-mihai.sain@microchip.com
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>

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Mihai Sain 2025-06-19 10:06:36 +03:00 • committed by Claudiu Beznea

parent 4101c8274b

commit 314862edb1

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arch/arm/boot/dts/microchip/sama7g5.dtsi

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