drm/i915/fbc: Reject PLANE_OFFSET.y%4!=0 on icl+ too

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icl and tgl are still affected by the modulo 4 PLANE_OFFSET.y
underrun issue. Reject such configurations on all gen9+ platforms.

Can be reproduced easily with the following sequence of
hardware poking:
while {
  write FBC_CTL.enable=1
  wait for vblank

  write PLANE_OFFSET .x=0 .y=32
  write PLANE_SURF
  wait for vblank

  # if PLANE_OFFSET.y is multiple of 4 the underrun won't happen
  write PLANE_OFFSET .x=0 .y=31
  write PLANE_SURF
  wait for vblank

  # extra vblank wait is required here presumably
  # to get FBC into the proper state
  wait for vblank

  write FBC_CTL.enable=0
  # underrun happens some time after FBC disable
  wait for vblank
}

Both 8888 and 565 pixel formats and all tilinga formats
seem affected. Reproduced on KBL/GLK/ICL/TGL. BDW confirmed
not affected.

Closes: https://gitlab.freedesktop.org/drm/intel/issues/792
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191213133453.22152-1-ville.syrjala@linux.intel.com
Reviewed-by: Imre Deak <imre.deak@intel.com>

...

This commit is contained in:

Ville Syrjälä 2019-12-13 15:34:48 +02:00

parent e1f0fbda75

commit 317b2cac79

1 changed files with 1 additions and 1 deletions

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drivers/gpu/drm/i915/display/intel_fbc.c

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