Amlogic clock updates for v5.6:

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* Add meson8b DDR clock controller
 * Add input clocks to meson8b controllers
 * Fix meson8b mali clock update using the glitch free mux
 * Fix pll driver division by zero init
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Merge tag 'clk-meson-v5.6-1' of https://github.com/BayLibre/clk-meson into clk-amlogic

Pull Amlogic clk driver updates from Jerome Brunet:

 - Add meson8b DDR clock controller
 - Add input clocks to meson8b controllers
 - Fix meson8b mali clock update using the glitch free mux
 - Fix pll driver division by zero init

* tag 'clk-meson-v5.6-1' of https://github.com/BayLibre/clk-meson:
  clk: clarify that clk_set_rate() does updates from top to bottom
  clk: meson: meson8b: make the CCF use the glitch-free mali mux
  clk: meson: pll: Fix by 0 division in __pll_params_to_rate()
  clk: meson: g12a: fix missing uart2 in regmap table
  clk: meson: meson8b: use of_clk_hw_register to register the clocks
  clk: meson: meson8b: don't register the XTAL clock when provided via OF
  clk: meson: meson8b: change references to the XTAL clock to use [fw_]name
  clk: meson: meson8b: use clk_hw_set_parent in the CPU clock notifier
  clk: meson: add a driver for the Meson8/8b/8m2 DDR clock controller
  dt-bindings: clock: meson8b: add the clock inputs
  dt-bindings: clock: add the Amlogic Meson8 DDR clock controller binding

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This commit is contained in:

Stephen Boyd 2020-01-17 11:01:09 -08:00

parent e42617b825 64c76b3177

commit 31ef091770

9 changed files with 291 additions and 56 deletions

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50

Documentation/devicetree/bindings/clock/amlogic,meson8-ddr-clkc.yaml

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5

Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt

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2

drivers/clk/meson/Makefile

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9

drivers/clk/meson/clk-pll.c

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1

drivers/clk/meson/g12a.c

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149

drivers/clk/meson/meson8-ddr.c

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124

drivers/clk/meson/meson8b.c

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4

include/dt-bindings/clock/meson8-ddr-clkc.h

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3

include/linux/clk.h

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