dmaengine: dw-edma: Improve the linked list and data blocks definition

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In the previous implementation, the driver assumed that there existed
only two memory spaces that would equally distribute the amount of
read/write channels.

This might not be the case on some other implementations, therefore this
patch change this requirement so that each write/read channel has
its own linked list and data space well defined, which allows
different sizes and locations.

Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
Link: https://lore.kernel.org/r/2e316cb983f8a1e09ce929029f87619dc92a52de.1613674948.git.gustavo.pimentel@synopsys.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

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Gustavo Pimentel 2021-02-18 20:04:03 +01:00 • committed by Vinod Koul

parent f3167dc163

commit 31fb8c1ff9

3 changed files with 160 additions and 85 deletions

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51

drivers/dma/dw-edma/dw-edma-core.c

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9

drivers/dma/dw-edma/dw-edma-core.h

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185

drivers/dma/dw-edma/dw-edma-pcie.c

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