clk: rockchip: rk3588: fix pclk_vo0grf and pclk_vo1grf

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Currently pclk_vo1grf is not exposed, but it should be referenced
from the vo1_grf syscon, which needs it enabled. That syscon is
required for HDMI RX and TX functionality among other things.

Apart from that pclk_vo0grf and pclk_vo1grf are both linked gates
and need the VO's hclk enabled in addition to their parent clock.

No Fixes tag has been added, since the logic requiring these clocks
is not yet upstream anyways.

Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Link: https://lore.kernel.org/r/20240126182919.48402-5-sebastian.reichel@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

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This commit is contained in:

Sebastian Reichel 2024-01-26 19:18:25 +01:00 • committed by Heiko Stuebner

parent 0fa04984a4

commit 326be62eaf

1 changed files with 4 additions and 6 deletions

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drivers/clk/rockchip/clk-rk3588.c

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