Improve the clocks for the rk3568 display outputs (parenting, pll-rates),

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use of_device_get_match_data() instead of open-coding on rk3568
 and reintroduce the expected fractional-divider behaviour that disappeared
 with the addition of CLK_FRAC_DIVIDER_POWER_OF_TWO_PS.
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Merge tag 'v5.18-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-rockchip

Pull Rockchip clk driver updates from Heiko Stuebner:

 - Improve the clocks for the rk3568 display outputs (parenting, pll-rates)
 - Use of_device_get_match_data() instead of open-coding on rk3568
 - Reintroduce the expected fractional-divider behaviour that disappeared
   with the addition of CLK_FRAC_DIVIDER_POWER_OF_TWO_PS

* tag 'v5.18-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  clk: rockchip: re-add rational best approximation algorithm to the fractional divider
  clk/rockchip: Use of_device_get_match_data()
  clk: rockchip: Add CLK_SET_RATE_PARENT to the HDMI reference clock on rk3568
  clk: rockchip: drop CLK_SET_RATE_PARENT from dclk_vop* on rk3568
  clk: rockchip: Add more PLL rates for rk3568

...

This commit is contained in:

Stephen Boyd 2022-03-09 10:47:28 -08:00

parent e783362eb5 10b74af310

commit 328212de9f

2 changed files with 15 additions and 8 deletions

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20

drivers/clk/rockchip/clk-rk3568.c

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3

drivers/clk/rockchip/clk.c

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