drm/i915/psr: Configure PIPE_SRCSZ_ERLY_TPT for psr2 early transport

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There is a new register used to configure selective update area size
for early transport.

Configure PIPE_SRCSZ_ERLY_TPT using calculated selective update area
carried in crtc_state->su_area.

Bspec: 68927

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20231218175004.52875-6-jouni.hogander@intel.com

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This commit is contained in:

Jouni Högander 2023-12-18 19:50:02 +02:00

parent 7f85883e4a

commit 3291bbb93e

2 changed files with 15 additions and 0 deletions

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10

drivers/gpu/drm/i915/display/intel_display.c

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5

drivers/gpu/drm/i915/display/intel_psr_regs.h

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