drm/i915/mtl: Skip PLL state verification in TBT mode

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In TBT-alt mode the driver doesn't program the PHY's PLL, which is
handled instead by Thunderbolt driver/FW components, hence the PLL's HW
vs. SW state verification should be skipped. During HW readout set a flag
in the PLL state if the port was at the moment in TBT-alt mode and skip
the verification of PLL parameters in this case.

Fixes: 45fe957ae7 ("drm/i915/display: Add compare config for MTL+ platforms")
Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11258
Cc: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240626170813.806470-1-imre.deak@intel.com

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This commit is contained in:

Imre Deak 2024-06-26 20:08:13 +03:00

parent a9422ec92a

commit 32a120f52a

3 changed files with 12 additions and 8 deletions

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13

drivers/gpu/drm/i915/display/intel_cx0_phy.c

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8

drivers/gpu/drm/i915/display/intel_ddi.c

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1

drivers/gpu/drm/i915/display/intel_dpll_mgr.h

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