RISC-V: Preliminary Perf Support

The RISC-V ISA defines a core set of performance counters that must exist on all processors along with a standard way to add more performance counters. This patch set adds preliminary perf support for RISC-V systems. Long term we'll move to model where all PMUs can be built into the kernel at the same time, detected at runtime (possibly via device tree), and provided to userspace. Since we currently only support the ISA-mandated performance counters there's no need to detect anything right now. Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2026-11-15 19:56:03 +00:00 · 2018-06-04 14:03:18 -07:00 · 2018-06-04 14:03:18 -07:00 · 32c81bced3
commit 32c81bced3
parent ebcbd75e39 0d431558d7
6 changed files with 835 additions and 0 deletions
--- a/Documentation/riscv/pmu.txt
+++ b/Documentation/riscv/pmu.txt
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
--- a/arch/riscv/include/asm/Kbuild
+++ b/arch/riscv/include/asm/Kbuild
--- a/arch/riscv/include/asm/perf_event.h
+++ b/arch/riscv/include/asm/perf_event.h
--- a/arch/riscv/kernel/Makefile
+++ b/arch/riscv/kernel/Makefile
--- a/arch/riscv/kernel/perf_event.c
+++ b/arch/riscv/kernel/perf_event.c