clk: qcom: ipq8074: fix missing GPLL0 divider width

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GPLL0 uses 4 bits post divider which should be specified
in clock driver structure.

Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

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Abhishek Sahu 2017-12-13 19:55:34 +05:30 • committed by Stephen Boyd

parent df96401649

commit 32cae024f7

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drivers/clk/qcom/gcc-ipq8074.c

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