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dmaengine: tegra210-adma: Override ADMA FIFO size

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ADMAIF FIFO uses a ring buffer and it is divided amongst the available
channels. The default FIFO size (in multiples of 16 words) of ADMAIF TX/RX
channels is as below:
 * On Tegra210,
     channel 1 to 2 : size = 3
     channel 3 to 10: size = 2
 * On Tegra186 and later,
     channel 1 to 4 : size = 3
     channel 5 to 20: size = 2

As per recommendation from HW, FIFO size of ADMA channel should be same as
the corresponding ADMAIF channel it maps to. FIFO corruption is observed if
the sizes do not match. We are using the default FIFO sizes for ADMAIF and
there is no plan to support any custom values.

Thus at runtime, override the ADMA channel FIFO size value depending on the
corresponding ADMAIF channel.

Signed-off-by: Sameer Pujar <spujar@nvidia.com>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Link: https://lore.kernel.org/r/1631722025-19873-4-git-send-email-spujar@nvidia.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Sameer Pujar 2021-09-15 21:37:05 +05:30 • committed by Vinod Koul
commit 32de4745e2
1 changed files with 34 additions and 14 deletions
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