clk: hi3798cv200: correct parent mux clock for 'clk_sdio0_ciu'

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Other than 'mmc_mux', 'clk_sdio0_ciu' uses a different parent mux clock.
Let's add this mux clock as 'sdio0_mux', and correct the parent of
'clk_sdio0_ciu' to be it.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

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Shawn Guo 2017-09-27 11:59:40 -07:00 • committed by Stephen Boyd

parent 90c42090c0

commit 3320f39bee

1 changed files with 11 additions and 1 deletions

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drivers/clk/hisilicon/crg-hi3798cv200.c

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