dt-bindings: iommu: riscv: Add bindings for Tenstorrent RISC-V IOMMU

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Extend the binding to cover details specific to the Tenstorrent RISC-V
IOMMU. In particular, a second register range is added which contains
M-privileged registers, e.g., PMAs and PMPs.

The RISC-V spec S-privileged registers remain in the first register
range and are compatible with "riscv,iommu" so the Linux driver does not
notice any difference, but the binding will be used by OpenSBI and
potentially other M-mode software.

Reviewed-by: Joel Stanley <joel@jms.id.au>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Joerg Roedel <joerg.roedel@amd.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
[fustini: fix dt_binding_check errors]
Signed-off-by: Drew Fustini <fustini@kernel.org>

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Nicholas Piggin 2026-05-21 10:06:33 -07:00 • committed by Drew Fustini

parent 0e400da642

commit 33583baeb1

1 changed files with 51 additions and 8 deletions

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Documentation/devicetree/bindings/iommu/riscv,iommu.yaml

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