drm/i915/icl: Define data/clock lanes dphy timing registers

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This patch defines DSI_CLK_TIMING_PARAM, DPHY_CLK_TIMING_PARAM,
DSI_DATA_TIMING_PARAM, DPHY_DATA_TIMING_PARAM register used in
dphy programming.

v2: Define mask/shift for bitfields and keep names as per BSPEC (Jani N)

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1537095223-5184-6-git-send-email-madhav.chauhan@intel.com

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Madhav Chauhan 2018-09-16 16:23:28 +05:30 • committed by Jani Nikula

parent 7a90938332

commit 33868a91c1

1 changed files with 58 additions and 0 deletions

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drivers/gpu/drm/i915/i915_reg.h

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