drm/i915: Implement workaround for CDCLK PLL disable/enable

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It was reported that we might get a hung and loss of register access in
some cases when CDCLK PLL is disabled and then enabled, while squashing
is enabled.
As a workaround it was proposed by HW team that SW should disable squashing
when CDCLK PLL is being reenabled.

v2: - Added WA number comment(Rodrigo Vivi)

Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230130135836.12738-1-stanislav.lisovskiy@intel.com

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Stanislav Lisovskiy 2023-01-30 15:58:36 +02:00

parent 9c608cf39b

commit 33d0c67dcb

1 changed files with 13 additions and 2 deletions

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15

drivers/gpu/drm/i915/display/intel_cdclk.c

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