clk: gxbb: add the SAR ADC clocks and expose them

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The HHI_SAR_CLK_CNTL contains three SAR ADC specific clocks:
- a mux clock to choose between different ADC reference clocks (this is
  2-bit wide, but the datasheet only lists the parents for the first
  bit)
- a divider for the input/reference clock
- a gate which enables the ADC clock

Additionally this exposes the ADC core clock (CLKID_SAR_ADC) and
CLKID_SANA (which seems to enable the analog inputs, but unfortunately
there is no documentation for this - we just mimic what the vendor
driver does).

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Tested-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>

...

This commit is contained in:

Martin Blumenstingl 2017-01-19 15:58:20 +01:00 • committed by Kevin Hilman

parent 0264a88d61

commit 33d0fcdfe0

3 changed files with 58 additions and 3 deletions

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48

drivers/clk/meson/gxbb.c

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9

drivers/clk/meson/gxbb.h

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4

include/dt-bindings/clock/gxbb-clkc.h

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