[POWERPC] 4xx: 440EPx/GRx incorrect write to DDR SDRAM errata workaround

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Add a workaround for PowerPC 440EPx/GRx incorrect write to
DDR SDRAM errata. Data can be written to wrong address
in SDRAM when write pipelining enabled on plb0. We disable
it in the cpu_setup for these processors at early init.

Signed-off-by: Valentine Barshak <vbarshak@ru.mvista.com>
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>

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Valentine Barshak 2007-09-22 00:50:09 +10:00 • committed by Josh Boyer

parent 8112753bb2

commit 340ffd267c

2 changed files with 27 additions and 1 deletions

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25

arch/powerpc/kernel/cpu_setup_44x.S

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3

arch/powerpc/kernel/cputable.c

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