drm/i915/vdsc: Account for DSC slice overhead in intel_vdsc_min_cdclk()

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When DSC is enabled on a pipe, the pipe pixel rate input to the
CDCLK frequency and pipe joining calculation needs an adjustment to
account for compression overhead "bubbles" added at each horizontal
slice boundary.

Account for this overhead while computing min cdclk required for DSC.

v2:
 - Get rid of the scaling factor and return unchanged pixel-rate
   instead of 0.
v3:
 - Use mul_u32_u32() for the bubble-adjusted pixel rate to avoid 64x64
   multiplication and drop redundant casts in DIV_ROUND_UP_ULL(). (Imre)

Bspec:68912
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Link: https://patch.msgid.link/20251223150826.2591182-1-ankit.k.nautiyal@intel.com

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This commit is contained in:

Ankit Nautiyal 2025-12-23 20:38:26 +05:30

parent fb3fba6933

commit 345ad34565

1 changed files with 31 additions and 4 deletions

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drivers/gpu/drm/i915/display/intel_vdsc.c

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