clk: meson-g12a: add PCIE PLL clocks

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Add the PCIe reference clock feeding the USB3 + PCIE combo PHY.

This PLL needs a very precise register sequence to permit to be locked,
thus using the specific clk-pll pcie ops.

The PLL is then followed by :
- a fixed /2 divider
- a 5-bit 1-based divider
- a final /2 divider

This reference clock is fixed to 100MHz, thus only a single PLL setup
is added.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Jerome Brunet <jbrunet@baylibre.com>
Link: https://lkml.kernel.org/r/20190307141455.23879-4-narmstrong@baylibre.com

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This commit is contained in:

Neil Armstrong 2019-03-07 15:14:55 +01:00

parent 39b8500283

commit 34775209ba

2 changed files with 122 additions and 1 deletions

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118

drivers/clk/meson/g12a.c

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5

drivers/clk/meson/g12a.h

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