x86, cacheinfo: Fix dependency of AMD L3 CID

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L3 cache index disable code uses PCI accesses to AMD northbridge functions.
Currently the code is #ifdef CONFIG_CPU_SUP_AMD.
But it should be #if (defined(CONFIG_CPU_SUP_AMD) && defined(CONFIG_PCI))
which in the end is a dependency to K8_NB.

Signed-off-by: Andreas Herrmann <andreas.herrmann3@amd.com>
LKML-Reference: <20100917160744.GF4958@loge.amd.com>
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>

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Andreas Herrmann 2010-09-17 18:07:45 +02:00 • committed by H. Peter Anvin

parent 509344b8b4

commit 3518dd14ca

1 changed files with 4 additions and 4 deletions

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arch/x86/kernel/cpu/intel_cacheinfo.c

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