MIPS: R5000: Fix TLB hazard handling.

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R5000 and the Nevada CPUs (RM5230, RM5231, RM5260, RM5261, RM5270 and
RM5271) are basically the same CPU core and all are documented to require
two instructions separating a write to c0_pagemask, c0_entryhi, c0_entrylo0,
c0_entrylo1 or c0_index.

So far we were only providing on cycle before / after a TLBR/TLBWI
for R5000 but 3 cycles before and 1 cycles after for the Nevadas.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

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Ralf Baechle 2012-10-16 22:13:06 +02:00

parent 02a5417751

commit 359187d647

1 changed files with 8 additions and 15 deletions

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arch/mips/mm/tlbex.c

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