clk: renesas: r9a07g044: Add M3 Clock support

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Add support for M3 clock which is sourced from DSI divider connected
to PLL5_4 mux.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220430114156.6260-7-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

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Biju Das 2022-04-30 12:41:53 +01:00 • committed by Geert Uytterhoeven

parent 300d95c5bb

commit 359f10c1b0

1 changed files with 4 additions and 1 deletions

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drivers/clk/renesas/r9a07g044-cpg.c

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