From 35cf35e239477cb28e5f6ccd987933d70c21061f Mon Sep 17 00:00:00 2001 From: John Madieu Date: Mon, 25 May 2026 11:05:58 +0000 Subject: [PATCH] arm64: dts: renesas: rzv2h: Add audio clock inputs Model the optional external audio clock inputs as CPG input clocks for RZ/V2H family SoCs (RZ/V2H, RZ/V2N, RZ/G3E), allowing the Audio Clock Generator (ADG) to derive internal audio clocks from these external sources. The clock frequencies are board-specific and must be overridden in the board DTS files. Signed-off-by: John Madieu Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260525110603.4018170-4-john.madieu.xa@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 20 ++++++++++++++++++-- arch/arm64/boot/dts/renesas/r9a09g056.dtsi | 20 ++++++++++++++++++-- arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 20 ++++++++++++++++++-- 3 files changed, 54 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi index b48da8534a3d..be11cdde3cfe 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi @@ -21,6 +21,20 @@ clock-frequency = <0>; }; + audio_clkb: audio-b-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + audio_clkc: audio-c-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + /* * The default cluster table is based on the assumption that the PLLCA55 clock * frequency is set to 1.7GHz. The PLLCA55 clock frequency can be set to @@ -271,8 +285,10 @@ cpg: clock-controller@10420000 { compatible = "renesas,r9a09g047-cpg"; reg = <0 0x10420000 0 0x10000>; - clocks = <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>; - clock-names = "audio_extal", "rtxin", "qextal"; + clocks = <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>, + <&audio_clkb>, <&audio_clkc>; + clock-names = "audio_extal", "rtxin", "qextal", + "audio_clkb", "audio_clkc"; #clock-cells = <2>; #reset-cells = <1>; #power-domain-cells = <0>; diff --git a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi index d6c8c39df2a4..3a308dbf733c 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi @@ -39,6 +39,20 @@ clock-frequency = <0>; }; + audio_clkb: audio-b-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + audio_clkc: audio-c-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + /* * The default cluster table is based on the assumption that the PLLCA55 clock * frequency is set to 1.7GHz. The PLLCA55 clock frequency can be set to @@ -294,8 +308,10 @@ cpg: clock-controller@10420000 { compatible = "renesas,r9a09g056-cpg"; reg = <0 0x10420000 0 0x10000>; - clocks = <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>; - clock-names = "audio_extal", "rtxin", "qextal"; + clocks = <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>, + <&audio_clkb>, <&audio_clkc>; + clock-names = "audio_extal", "rtxin", "qextal", + "audio_clkb", "audio_clkc"; #clock-cells = <2>; #reset-cells = <1>; #power-domain-cells = <0>; diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi index 1e94366bb7ee..8af0f0f2f2f7 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi @@ -21,6 +21,20 @@ clock-frequency = <0>; }; + audio_clkb: audio-b-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + audio_clkc: audio-c-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + /* * The default cluster table is based on the assumption that the PLLCA55 clock * frequency is set to 1.7GHz. The PLLCA55 clock frequency can be set to @@ -276,8 +290,10 @@ cpg: clock-controller@10420000 { compatible = "renesas,r9a09g057-cpg"; reg = <0 0x10420000 0 0x10000>; - clocks = <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>; - clock-names = "audio_extal", "rtxin", "qextal"; + clocks = <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>, + <&audio_clkb>, <&audio_clkc>; + clock-names = "audio_extal", "rtxin", "qextal", + "audio_clkb", "audio_clkc"; #clock-cells = <2>; #reset-cells = <1>; #power-domain-cells = <0>;