ARM: dts: vexpress: Support GICC_DIR operations

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The GICv2 CPU interface registers span across 8K, not 4K as indicated in
the DT.  Only the GICC_DIR register is located after the initial 4K
boundary, leaving a functional system but without support for separately
EOI'ing and deactivating interrupts.

After this change the system supports split priority drop and interrupt
deactivation.

Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
[sudeep.holla@arm.com: included same fix for tc1 platform too]
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>

...

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Christoffer Dall 2016-12-10 21:13:51 +01:00 • committed by Sudeep Holla

parent 7ce7d89f48

commit 368400e242

2 changed files with 2 additions and 2 deletions

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arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts

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2

arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts

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