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iio: dac: ad5770r: Fix alignment for DMA safety
[ Upstream commit27f2261d16] ____cacheline_aligned is an insufficient guarantee for non-coherent DMA on platforms with 128 byte cachelines above L1. Switch to the updated IIO_DMA_MINALIGN definition. Fixes:cbbb819837("iio: dac: ad5770r: Add AD5770R support") Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Cc: Alexandru Tachici <alexandru.tachici@analog.com> Acked-by: Nuno Sá <nuno.sa@analog.com> Link: https://lore.kernel.org/r/20220508175712.647246-55-jic23@kernel.org Signed-off-by: Sasha Levin <sashal@kernel.org>
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