clk: rockchip: add flags for rk3328 dclk_lcdc

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dclk_lcdc can be sourced from a general pll source as well
as the hdmiphy's pll output. We will want to set this source
by hand (to the system-pll-source in most cases) and also
want rate changes to this clock to be able to also touch
the pll source clock if needed, so add CLK_SET_RATE_PARENT
and CLK_SET_RATE_NO_REPARENT for dclk_lcdc.

Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
[ammended commit message]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

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Zheng Yang 2017-05-25 18:00:24 +08:00 • committed by Heiko Stuebner

parent 7f872cb362

commit 36ec03618c

1 changed files with 1 additions and 1 deletions

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drivers/clk/rockchip/clk-rk3328.c

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