drm/i915/cx0: Fix port to PLL ID mapping on BMG

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The intel_port_to_tc() call in mtl_port_to_pll_id() assumed that all
TypeC DDI ports are connected to a TypeC PHY. This is not true on BMG
where all the ports - including the PORT_TC1..4 TypeC DDI ports - are
connected to a non-TypeC PHY. For these ports intel_port_to_tc()
returns TC_PORT_NONE, which results in an incorrect port -> PLL ID
mapping. Fix this up by using the expected PORT_TC1..4 port ->
TC_PORT_1..4 tc_port mapping on BMG as well.

Fixes: ca1eda5cd4 ("drm/i915/cx0: Add MTL+ .get_dplls hook")
Cc: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://patch.msgid.link/20251120172358.1282765-1-imre.deak@intel.com

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This commit is contained in:

Imre Deak 2025-11-20 19:23:54 +02:00

parent a5f0cc8e0c

commit 370f45b1ce

2 changed files with 9 additions and 7 deletions

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7

drivers/gpu/drm/i915/display/intel_ddi.c

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9

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

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