drm/amd/display: Implementing new bandwidth registers for DCE120

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Registers are added and defined.
Programmed to default values.
Stutter level watermark register is being set to calculated value.
Urgent level registers are programmed to the same as urgency.
The programming of the registers is not expected to have any
functional difference in performance.

Signed-off-by: Mikita Lipski <mikita.lipski@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

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Mikita Lipski 2018-02-21 16:57:10 -05:00 • committed by Alex Deucher

parent 6133470c8e

commit 3722c79464

5 changed files with 55 additions and 17 deletions

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58

drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c

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9

drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h

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3

drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

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1

drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c

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1

drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h

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