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ARM: dts: imx6qdl: Add Engicam i.Core 1.5 MX6
The 1.5 version of Engicam's i.Core MX6 CPU module features a different clock provider for the ethernet's PHY interface. Adjust the FEC ptp clock to reference CLK_ENET_REF clock source, and set SION bit of MX6QDL_PAD_GPIO_16__ENET_REF_CLK to adjust the input path of that pin. The newly introduced imx6ql-icore-1.5.dtsi allows to collect in a single place differences between version '1.0' and '1.5' of the module. Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Jacopo Mondi <jacopo@jmondi.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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