clk: renesas: r8a77970: Add SD0H/SD0 clocks for SDHI

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On R-Car V3M (AKA R8A77970), the SD0CKCR is laid out differently than on
the other R-Car gen3 SoCs. In fact, the layout is the same as on R-Car gen2
SoCs, so we'll need to copy the divisor tables from the R-Car gen2 driver.
We'll also need to support the SoC specific clock types, thus we're adding
CLK_TYPE_GEN3_SOC_BASE at the end of 'enum rcar_gen3_clk_types', declare
SD0H/SDH clocks in 'enum r8a77970_clk_types', and handle those clocks in
the overridden cpg_clk_register() method; then, finally, add the SD-IF
module clock (derived from the SD0 clock).

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

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Sergei Shtylyov 2018-09-01 23:12:28 +03:00 • committed by Geert Uytterhoeven

parent 0a87bf6cd5

commit 381081ffc2

2 changed files with 67 additions and 2 deletions

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66

drivers/clk/renesas/r8a77970-cpg-mssr.c

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3

drivers/clk/renesas/rcar-gen3-cpg.h

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