drm/amd/display: On clock init, maintain DISPCLK freq

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[Why]
On init if a display is connected, we need to maintain the DISPCLK
frequency Even though DPG_EN=1, the display still requires the correct
timing or it could cause audio corruption (if DISPCLK freq is reduced).

[How]
Read the current DISPCLK freq and request the same value to ensure the
timing is valid and unchanged.

Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Chris Park <chris.park@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

...

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Chris Park 2024-06-04 14:25:14 -04:00 • committed by Alex Deucher

parent 3a69c1702f

commit 3838c67365

2 changed files with 27 additions and 1 deletions

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17

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

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11

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

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