clk: ingenic: Don't use CLK_SET_RATE_GATE for PLL

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CLK_SET_RATE_GATE means that the clock must be gated when being
reclocked. This is not the case for the PLLs in Ingenic SoCs.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Link: https://lore.kernel.org/r/20200903015048.3091523-3-paul@crapouillou.net
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

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Paul Cercueil 2020-09-03 03:50:46 +02:00 • committed by Stephen Boyd

parent 21534fe39c

commit 3860dc599b

1 changed files with 7 additions and 2 deletions

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9

drivers/clk/ingenic/cgu.c

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