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OMAP3: PM: Fix for MPU power domain MEM BANK position

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MPU power domain bank 0 bits are displayed in position of bank 1
in PWRSTS and PREPWRSTS registers. So read them from correct
position

Signed-off-by: Thara Gopinath <thara@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
This commit is contained in:
Thara Gopinath 2009-12-08 16:33:15 -07:00 • committed by paul
commit 3863c74b51
3 changed files with 11 additions and 1 deletions
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