clk: sunxi-ng: a31: Correct lcd1-ch1 clock register offset

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The register offset for the lcd1-ch1 clock was incorrectly pointing to
the lcd0-ch1 clock. This resulted in the lcd0-ch1 clock being disabled
when the clk core disables unused clocks. This then stops the simplefb
HDMI output path.

Reported-by: Bob Ham <rah@settrans.net>
Fixes: c6e6c96d8f ("clk: sunxi-ng: Add A31/A31s clocks")
Cc: stable@vger.kernel.org # 4.9.x-
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

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Chen-Yu Tsai 2017-05-03 11:13:46 +08:00 • committed by Maxime Ripard

parent 2ea659a9ef

commit 38b8f82386

1 changed files with 1 additions and 1 deletions

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drivers/clk/sunxi-ng/ccu-sun6i-a31.c

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