From 390f58e29de3a3ddb05dd739a5fb12ed973d9088 Mon Sep 17 00:00:00 2001 From: Ping-Ke Shih Date: Tue, 7 Jul 2026 17:10:46 +0800 Subject: [PATCH] wifi: rtw89: 8922d: set TX compensation by format v2 The total number of TX compensation registers is 22, including 7 base and 15 ones according to operating channel. The v0 is 22 ones per channel. To reduce array size, v1 treats 7 base as common part across all conditions. However, we can fine tune the base part to yield better performance, so divide base into two sets according to NSS. Summarize dimensions as follows base (7) vals(15) v0 nss * band * path nss * band * path v1 1 nss * band * path v2 nss nss * band * path Currently, v1 and v2 can present in a file, but only one fw element with a specific format will be used for specific RFE type. Signed-off-by: Ping-Ke Shih Link: https://patch.msgid.link/20260707091056.42771-6-pkshih@realtek.com --- drivers/net/wireless/realtek/rtw89/rtw8922d.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/net/wireless/realtek/rtw89/rtw8922d.c b/drivers/net/wireless/realtek/rtw89/rtw8922d.c index 212917db7154..e8267173bd4c 100644 --- a/drivers/net/wireless/realtek/rtw89/rtw8922d.c +++ b/drivers/net/wireless/realtek/rtw89/rtw8922d.c @@ -2249,6 +2249,12 @@ static void rtw8922d_set_digital_pwr_comp(struct rtw89_dev *rtwdev, struct { __le32 vals[DIGITAL_PWR_COMP_VALS_NUM]; } sets[2][RTW89_TX_COMP_BAND_NR][BB_PATH_NUM_8922D]; + } *pwr_comp_v1; + const struct { + __le32 base[2][DIGITAL_PWR_COMP_BASE_NUM]; + struct { + __le32 vals[DIGITAL_PWR_COMP_VALS_NUM]; + } sets[2][RTW89_TX_COMP_BAND_NR][BB_PATH_NUM_8922D]; } *pwr_comp; struct rtw89_fw_elm_info *elm_info = &rtwdev->fw.elm_info; const struct rtw89_fw_element_hdr *txcomp_elm = elm_info->tx_comp; @@ -2259,8 +2265,12 @@ static void rtw8922d_set_digital_pwr_comp(struct rtw89_dev *rtwdev, if (sizeof(*pwr_comp) == le32_to_cpu(txcomp_elm->size)) { pwr_comp = (const void *)txcomp_elm->u.common.contents; - comp_base = &pwr_comp->base; + comp_base = &pwr_comp->base[nss]; comp_vals = &pwr_comp->sets[nss][chan->tx_comp_band][path].vals; + } else if (sizeof(*pwr_comp_v1) == le32_to_cpu(txcomp_elm->size)) { + pwr_comp_v1 = (const void *)txcomp_elm->u.common.contents; + comp_base = &pwr_comp_v1->base; + comp_vals = &pwr_comp_v1->sets[nss][chan->tx_comp_band][path].vals; } else if (sizeof(*pwr_comp_v0) == le32_to_cpu(txcomp_elm->size)) { pwr_comp_v0 = (const void *)txcomp_elm->u.common.contents; comp_base = &pwr_comp_v0->sets[nss][chan->tx_comp_band][path].base;