drm/i915/gen11: enable support for headerless msgs

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Setting bit5 (headerless msg for preemptible GPGPU context) of SAMPLER_MODE
register to enable support for the headless msgs on gen11. None of existing
use cases will be affected by this as this change makes both types of
message - headerless and w/ header supported at the same time. It also
complies with the new recommendation for the default bit value for the
next gen.

v2: rewrote commit message to include more information
v3: setting the bit in icl_ctx_workarounds_init()

Signed-off-by: Dongwon Kim <dongwon.kim@intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190425055005.21790-1-chris@chris-wilson.co.uk
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>

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Dongwon Kim 2019-04-25 06:50:05 +01:00 • committed by Chris Wilson

parent 63e8dcdb4f

commit 397049a030

2 changed files with 5 additions and 0 deletions

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4

drivers/gpu/drm/i915/gt/intel_workarounds.c

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1

drivers/gpu/drm/i915/i915_reg.h

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