drm/tegra: dc: Make sure to set the module clock rate

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When applying the PLL changes from the computed state object, make sure
to set the rate of the display controller module clock. Failing to do so
can yield to a situation where the parent will be set to the proper
pixel clock, but the module clock will be divided down to the rate that
is happened to be set to before the parent rate change.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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Thierry Reding 2017-08-30 17:38:39 +02:00

parent a4bfa0961c

commit 39e08affec

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drivers/gpu/drm/tegra/dc.c

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