perf/x86/intel: Add simple Haswell PMU support

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Similar to SandyBridge, but has a few new events and two
new counter bits.

There are some new counter flags that need to be prevented
from being set on fixed counters, and allowed to be set
for generic counters.

Also we add support for the counter 2 constraint to handle
all raw events.

(Contains fixes from Stephane Eranian.)

Reviewed-by: Stephane Eranian <eranian@google.com>
Signed-off-by: Andi Kleen <ak@linux.intel.com>
Cc: Andi Kleen <ak@linux.jf.intel.com>
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
Link: http://lkml.kernel.org/r/1371515812-9646-3-git-send-email-andi@firstfloor.org
Signed-off-by: Ingo Molnar <mingo@kernel.org>

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This commit is contained in:

Andi Kleen 2013-06-17 17:36:48 -07:00 • committed by Ingo Molnar

parent 130768b8c9

commit 3a632cb229

3 changed files with 91 additions and 2 deletions

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3

arch/x86/include/asm/perf_event.h

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5

arch/x86/kernel/cpu/perf_event.h

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85

arch/x86/kernel/cpu/perf_event_intel.c

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