drm/xe: Move register MMIO into xe_tile

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Each tile has its own register region in the BAR, containing instances
of all registers for the platform.  In contrast, the multiple GTs within
a tile share the same MMIO space; there's just a small subset of
registers (the GSI registers) which have multiple copies at different
offsets (0x0 for primary GT, 0x380000 for media GT).  Move the register
MMIO region size/pointers to the tile structure, leaving just the GSI
offset information in the GT structure.

Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://lore.kernel.org/r/20230601215244.678611-7-matthew.d.roper@intel.com
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

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This commit is contained in:

Matt Roper 2023-06-01 14:52:19 -07:00 • committed by Rodrigo Vivi

parent 3643e63715

commit 3b0d4a5579

5 changed files with 51 additions and 24 deletions

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16

drivers/gpu/drm/xe/xe_device_types.h

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3

drivers/gpu/drm/xe/xe_ggtt.c

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9

drivers/gpu/drm/xe/xe_gt_types.h

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26

drivers/gpu/drm/xe/xe_mmio.c

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21

drivers/gpu/drm/xe/xe_mmio.h

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