clk: renesas: r8a779a0: Fix CANFD parent clock

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According to Figure 52A.1 ("RS-CANFD Module Block Diagram (in classical
CAN mode)") in the R-Car V3U Series User’s Manual Rev. 0.5, the parent
clock for the CANFD peripheral module clock is the S3D2 clock.

Fixes: 9b621b6adf ("clk: renesas: r8a779a0: Add CANFD module clock")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/aef9300f44c9141b1465343f91c5cc7303249b6e.1713279523.git.geert+renesas@glider.be

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Geert Uytterhoeven 2024-04-16 17:00:51 +02:00

parent c0516eb4cf

commit 3b23118bdb

1 changed files with 1 additions and 1 deletions

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drivers/clk/renesas/r8a779a0-cpg-mssr.c

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