net/mlx5: Adjustments for the activate LAG logic to run under sriov

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When HW lag is set/unset, roce must not be enabled on the port, as such
we wrap such changes with roce enable/disable either directly or through
re-creation of IB device.

Currently, lag and sriov are mutually exclusive, so by definition this
code doesn't run under sriov.

Towards changing this exclusion, we need to make sure that roce will not
be enabled on the eswitch manager port under sriov since this is
requirement of the switchdev mode.

We are going strict here and avoiding this all together under sriov.

Signed-off-by: Rabie Loulou <rabiel@mellanox.com>
Reviewed-by: Or Gerlitz <ogerlitz@mellanox.com>
Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>

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Rabie Loulou 2018-04-26 16:45:41 +03:00 • committed by Saeed Mahameed

parent 1418ddd96a

commit 3b5ff59fd8

1 changed files with 21 additions and 12 deletions

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drivers/net/ethernet/mellanox/mlx5/core/lag.c

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