ARM: i.MX6Q: correct emi_sel clock muxing

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The correct muxing for emi_sel clock should be
2b'00 - 396M PFD
2b'01 - PLL3
2b'10 - AXI clk root
2b'11 - 352M PFD

This patch corrects the muxing in the clock driver.

Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Dirk Behme <dirk.behme@de.bosch.com>

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Liu Ying 2013-07-03 15:29:06 +08:00 • committed by Shawn Guo

parent ceac9b9214

commit 3b79cd15bf

1 changed files with 3 additions and 2 deletions

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arch/arm/mach-imx/clk-imx6q.c

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