MIPS: cmpxchg: Implement 1 byte & 2 byte cmpxchg()

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Implement support for 1 & 2 byte cmpxchg() using read-modify-write atop
a 4 byte cmpxchg(). This allows us to support these atomic operations
despite the MIPS ISA only providing 4 & 8 byte atomic operations.

This is required in order to support queued rwlocks (qrwlock) in a later
patch, since these make use of a 1 byte cmpxchg() in their slow path.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/16355/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

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Paul Burton 2017-06-09 17:26:40 -07:00 • committed by Ralf Baechle

parent b70eb30056

commit 3ba7f44d2b

2 changed files with 64 additions and 0 deletions

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7

arch/mips/include/asm/cmpxchg.h

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57

arch/mips/kernel/cmpxchg.c

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