arm: zynq: Label whole PL part as fpga_full region

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This will simplify dt overlay structure for the whole PL.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

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Michal Simek 2017-02-14 17:40:21 +01:00

parent e5e6f6872c

commit 3c220bf420

1 changed files with 8 additions and 0 deletions

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arch/arm/boot/dts/zynq-7000.dtsi

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